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Digital systems design using Verilog

Digital systems design using Verilog
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Barcode Shelf Location Collection Volume Ref. Branch Status Due Date Res.
10029170 TK7885.7.R68 2016
 Computer Science   GUtech Library . . Available .  
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Field name Details
ISBN 9781305120747
Language E
Shelf Location TK7885.7.R68 2016
Author Roth, Charles H
Title Digital systems design using Verilog
Int'l ed.
Publisher [Boston, Massachusetts] : Cengage Learning , 2016
Description x, 582 pages : illustrations ; 23 cm
Specific Type of Material Book
Contents 1. REVIEW OF LOGIC DESIGN FUNDAMENTALS.Combinational Logic. Boolean Algebra and Algebraic Simplification. Karnaugh Maps. Designing with NAND and NOR Gates. Hazards in Combinational Circuits. Flip-Flops and Latches. Mealy Sequential Circuit Design. Design of a Moore Sequential Circuit. Equivalent States and Reduction of State Tables. Sequential Circuit Timing. Tristate Logic and Busses.2. INTRODUCTION TO VERILOG.Computer-Aided Design. Hardware Description Languages. Verilog Description of Combinational Circuits. Verilog Modules. Verilog Assignments. Procedural Assignments. Modeling Flip-Flops Using Always Block. Always Blocks Using Event Control Statements. Delays in Verilog. Compilation, Simulation, and Synthesis of Verilog Code. Verilog Data Types and Operators. Simple Synthesis Examples. Verilog Models for Multiplexers. Modeling Registers and Counters Using Verilog Always Statements. Behavioral and Structural Verilog. Constants. Arrays. Loops in Verilog. Testing Verilog Model. A Few Things to Remember.3. INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES.Brief Overview of Programmable Logic Devices. Simple Programmable Logic Devices (SPLDs). Complex Programmable Logic Devices (CPLDs). Field-Programmable Gate Arrays (FPGAs).4. DESIGN EXAMPLES.BCD to 7-Segment Display Decoder. A BCD Adder. 32-Bit Adders. Traffic Light Controller. State Graphs for Control Circuits. Scoreboard and Controller. Synchronization and Debouncing. A Shift-and-Add Multiplier. Array Multiplier. A Signed Integer/Fraction Multiplier. Keypad Scanner. Binary Dividers.5. SM CHARTS AND MIRCOPROGRAMMING.State Machine Charts. Derivation of SM Charts. Realization of SM Charts. Implementation of the Dice Game. Microprogramming. Linked State Machines.6. DESIGNING WITH FIELD PROGRAMMABLE GATE ARRAYS.Implementing Functions in FPGAs. Implementing Functions Using Shannon's Decomposition. Carry Chains in FPGAs. Cascade Chains in FPGAs. Examples of Logic Blocks in Commercial FPGAs. Dedicated Memory in FPGAs. Dedicated Multipliers in FPGAs. Cost of Programmability. FPGAs and One-Hot State Assignment. FPGA Capacity: Maximum Gates versus Usable Gates. Design Translation (Synthesis). Mapping, Placement, and Routing.7. FLOATING-POINT ARITHMETIC.Representation of Floating-Point Numbers. Floating-Point Multiplication. Floating-Point Addition. Other Floating-Point Operations.8. ADDITIONAL TOPICS IN VERILOG.Verilog Functions. Verilog Tasks. Multi-Valued Logic and Signal Resolution. Built-in Primitives. User Defined Primitives. SRAM Model. Model for SRAM Read/Write System. Rise and Fall Delays of Gates. Named Association. Generate Statements. System Functions. Compiler Directives. File I/O Functions. Timing Check.9. DESIGN OF A RISC MICROPROCESSOR.The RISC Philosophy. The MIPS ISA. MIPS Instruction Encoding. Implementation of a MIPS Subset. VHDL Model.10. HARDWARE TESTING AND DESIGN FOR TESTABILITY.Testing Combinational Logic. Testing Sequential Logic. Scan Testing. Boundary Scan. Built-In Self-Test.
Subject Verilog (Computer hardware description language)
Digital integrated circuits --Design and construction
Other name(s) Lizy Kurian John; Byeong Kil Lee
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